Open-source research like the CMC standard codes is less celebrated than the commercial successes of closed innovations. Open innovation, nonetheless, is an important driver of digital technologies. Prof. Don Pederson, starting with his SPICE, built a culture of open-sourcing the university's research at UC Berkeley. That open EDA research tradition continues with BSIM and the Berkeley RISC. It has also influenced the successful spread of FinFET. A good balance between open and closed innovations is important to the advancement and safety of technology. 

At this point in history, most ESD specialists believe that the physics underlying ESD device behavior are understood and can be expressed in the form of a compact model. Optimizing and validating those models remains a challenge and will be the main focus of this presentation. However, for the benefit of non-ESD specialists, the talk will start with a brief introduction to CMOS ESD protection devices and their behavior.

Ordinarily, compact model parameter extraction utilizes DC and C-V measurement data; in some cases, the dataset may be augmented by S-parameter data. All those measurements use common laboratory equipment, and consistent results are obtained in different laboratories.

This talk brings out the shortfalls of conventional textbook modeling of p-n junctions and MOSFETs, then goes over more elaborate models that can deal with those problems. For p-n junctions, the conventional depletion approximation only works for forward bias voltages below the built-in potential. For MOSFETs, the commonly practiced gradual channel approximation (GCA) fails in the velocity saturation region. It is shown that the conventional terms of pinch-off and channel length modulation are misleading. A non-GCA MOSFET model that takes the potential curvature in the source-drain direction into account is described. It generates continuous current-voltage solutions from the triode region into the velocity saturation region with finite output conductance. Lastly, the concept of “threshold voltage” is investigated by examining the Q_i-V_gs characteristics of an undoped double-gate MOSFET as a function of temperature. An unambiguously defined threshold voltage emerges when the electron thermal energy is diminished.      

Modern discrete power devices such as SiC MOSFETs presents significant modeling and simulation challenges, motivating the need for accurate, physics-based SPICE models to achieve first-time-right system design. This paper outlines a SPICE-agnostic approach for implementing nonlinear electrical behavior, scalable geometry equations, and correct thermal-impedance modelling suitable for discrete devices and power modules. A unified characterization flow is presented that incorporates pulsed I–V, short-circuit waveforms, and detailed parasitic extraction to accurately predict switching performance and energy losses. The resulting methodology supports reliable electrical-thermal simulation and enables robust virtual prototyping for next-generation power-electronics applications. 

Charge capture and emission by defects (traps) close to the conduction channel is a major source of noise and aging in modern electron devices. A comprehensive physics-based modeling and simulation approach for Bias Temperature Instability (BTI), Random Telegraph Noise (RTN) and low-frequency (1/f) noise is reviewed, discussed and summarized. It allows for the derivation of analytical formulations for 1/f noise (frequency domain), RTN (time domain) and BTI (aging) using a single modeling framework, where model parameters are the same in frequency and time domain. Operation under cyclo-stationary conditions is also modeled.

This review surveys recent advances in the application of artificial intelligence (AI) and machine learning (ML) within the compact modeling domain for integrated circuits. Neural network (NN) compact models, including pure NN, compensation NN, and knowledge-based NN, are briefly discussed, with emphasis on the recently developed physics-enhanced neural networks (PENN). PENN incorporates physics into its NN formulation, enabling modeling of process variation (PV) and local layout effects (LLE) through physical model parameters in preprocessing and postprocessing. The review also covers ML-assisted model parameter (MP) extraction, highlighting multi-stage and reinforcement learning strategies for scalability and adaptability. Transient circuit simulation, emerging memory, and aging models are addressed using recurrent neural networks (RNN), while variation and layout effects are explored through weight perturbations and variational autoencoders. As device complexity increases, the integration of AI and ML is expected to play a critical role in advancing reliable simulation and innovation in compact modeling.

Accurate ESD compact models are essential for designing robust on-chip protection in advanced CMOS technologies. This work presents three case studies showing how calibrated ESD models enable reliable prediction of stress voltages and guide optimization of ESD protection networks. The results demonstrate that standardized, measurement-based ESD models are critical for achieving required ESD performance levels in modern IC designs.

In this invited paper, we discuss several compact modeling approaches for ferroelectric memory devices. A novel sub-circuit extends the single-domain Landau-Khalatnikov equation to consider ferroelectric capacitors with multiple domains and can explain the special transient waveform we have measured. To model FE FETs as synaptic device in the context of online neural network (NN) training, on the other hand, simple BSIM-based expressions for Id-Vgs for various programmed states is adopted. NN inference accuracy as function of temperature, bias voltage, in the presence of device variation, and over time after retention degradation, are all captured with the model. Finally, the nucleation-limited switching (NLS) model captures minor loops and frequency dependence better in a physical manner, although the simulation time is found to be significantly longer. With the NLS model we demonstrated the simulation of recall operation for non-volatile SRAM (NV-SRAM). A special recall scheme, where the voltage of the plate-line is raised before the supply voltage is, allows for better design margin during recall operation, and reduces area requirements for NV-SRAM.

The semiconductor industry increasingly relies on Machine Learning (ML) techniques to drive advancements in efficiency and capability. This article introduces a Compensation-based MOSFET model framework, distinguished by its extendibility based on existing physics-based model equations. In addition to this core MOSFET model, we will present Convolutional-based layout extraction methodologies tailored for intricate multi-physics simulations. A key focus of this work will also be the demonstrated benefits of these ML-oriented solutions within the design sign-off flow. The evolution of SPICE platforms is significantly aided by the TSMC Model Interface (TMI/TMI-RC), which has pioneered close collaborations with Electronic Design Automation (EDA) partners, contributing to the progress of the entire semiconductor community.

Scalable solid-state quantum computation demands integration of quantum system with digital and analog electronics. This needs to be achieved at deep-cryogenic temperatures (≤10K) and within constrained power and noise budgets to protect the quantum information from decoherence. Leveraging quantum phenomena may help alleviate such challenges, enabling ultra-low-power hybrid quantum-classical microwave circuits for qubit control and readout. We presents novel compact modeling of quantum systems that recasts the quantum dynamics into coupled differential equations compatible with the standard modified nodal analysis used by electrical circuit simulators, and present the implementation of qubit models in Verilog-A demonstrating accurate representation of coherent quantum phenomena. This work paves the way for the use of standard EDA tools in the field of quantum technologies to simulate the behavior of pure quantum and quantum-classical hybrid circuits.